1. Field of the Invention
The invention relates to testing of semiconductor devices, and more particularly to automated placement of markers for identifying and analyzing critical paths in the routing of integrated circuits.
2. Description of the Related Art
Integrated circuits have become key components of many consumer and commercial electronic products, often replacing discrete components and enhancing product functionality. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuits (also referred to as "chips") may use many functions that previously could not be implemented onto a single chip, including microprocessors, digital signal processors, mixed signal and analog functions, large blocks of memory and high speed interfaces. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. However, the complex nature of today's integrated circuits present new testing challenges.
Another difficult task facing integrated circuit manufacturers is interconnecting the millions of gates and megabytes of memory that may be present on a chip. To aid in this task, new metallization schemes have been developed that allow five or more levels of interconnections, with pitches of 0.125 .mu.m and tighter on the first few layers. Additionally, new planarization procedures such as chemical-mechanical polishing help to flatten the insulating oxide layers between the metal layers in order to provide an even surface for subsequent lithography steps. These techniques eliminate potential optical distortion that may occur when subsequent layer patterns are formed using photolithographic techniques. Flatter surfaces allow finer dimensions to be created.
As semiconductor processes migrate into the deep submicron range with multiple metal layers, increased circuit speeds effectively turn metal routing lines (or interconnect) into active components. The large area required by today's integrated circuits usually means that the performance of the integrated circuitry can be dominated by propagation delays through longer metal routing lines rather than the basic gate delays of individual logic elements. This phenomenon is exacerbated by the fact that as the width of a wire shrinks, the resistance of the wire increases more rapidly than capacitance decreases. It has been estimated, for example, that interconnect determines as much as 80% of the total delay in integrated circuits implemented in 0.25 .mu.m process rules. An increase in average propagation delays may result in a greater number of critical timing paths (e.g., paths in which best or worst case simulated propagation delays may approach the limits required for proper functionality). Most timing problems involve such critical timing paths.
Further, in deep submicron designs, crosstalk between metal layers also becomes a consideration. Crosstalk between the metal interconnects of critical timing paths may cause a wrong logic result during a particular clock cycle, and may also effect the timing behavior of neighboring lines, particularly in critical timing paths.
When performing timing analysis on a typical integrated circuit design, verification and synthesis tools estimate timing using floorplan or layout-based delay information supplied via back-annotation. For example, synthesis and floorplanning tools are commonly used to identify critical timing paths, while layout parasitic extraction (LPE) tools in conjunction with proprietary technology libraries are used to estimate the delay each critical path will experience in final layout. Functional simulations are often performed using these estimated delay values to verify operability. The terms "floorplan" and "layout" refer to the physical geometry of an integrated circuit or die. A layout is represented by a layout database containing information for generating the masks used to fabricate integrated circuits.
Despite the use of sophisticated verification tools, critical timing paths do not always perform as expected when the completed integrated circuit is tested. Propagation delays through critical paths sometimes vary from simulated values for any of a number of reasons. One method of testing for and debugging timing faults in critical timing paths involves the use of probe equipment. Such equipment can take a variety of forms, including ion/electron beam and mechanical probing. Probes function to make electrical contact with a specific portion of an integrated circuit so that voltages or currents can be applied or measured to test for functionality. Integrated structures capable of functioning as probe points have been included in integrated circuits in the past. Such probe points are typically enlarged metal areas that are integral with a metal routing line and aid in the probing process. Probe points are often inserted into integrated circuit designs only after a problem has been detected in prototype devices.
In today's deep submicron designs, however, thorough probing verification and electrical failure analysis is limited by the difficulty in identifying critical paths and the inaccessibility of buried electrical nodes. A product engineer or failure analysis engineer confronted with the task of identifying critical timing paths must expend considerable time locating the metal routing lines of the path since the majority of signal lines appear similar when viewed under magnification. Locating a specific path generally involves the use of simulation and layout tools, test results, and navigational systems, and may also involve consultation with design engineers and application engineers.